//****************************************************************************** // MSP430xG46x Demo - USCI_A0, 115200 UART Echo ISR, DCO SMCLK // // Description: Echo a received character, RX ISR used. Normal mode is LPM0. // USCI_A0 RX interrupt triggers TX Echo. // Baud rate divider with 1048576hz = 1048576/115200 = ~9.1 (009h|01h) // ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = default DCO = 32 x ACLK = 1048576Hz // //* An external watch crystal between XIN & XOUT is required for ACLK *// // // MSP430xG461x // ----------------- // /|\| XIN|- // | | | 32kHz // --|RST XOUT|- // | | // | P4.6/UCA0TXD|------------> // | | 115200 - 8N1 // | P4.7/UCA0RXD|<------------ // // K. Quiring/ M. Mitchell // Texas Instruments Inc. // October 2006 // Built with IAR Embedded Workbench Version: 3.41A //****************************************************************************** void main(void) { volatile unsigned int i; WDTCTL = WDTPW+WDTHOLD; // Stop WDT FLL_CTL0 |= XCAP14PF; // Configure load caps do { IFG1 &= ~OFIFG; // Clear OSCFault flag for (i = 0x47FF; i > 0; i--); // Time for flag to set } while ((IFG1 & OFIFG)); // OSCFault flag still set? P4SEL |= 0x0C0; // P4.7,6 = USCI_A0 RXD/TXD UCA0CTL1 |= UCSSEL_2; // SMCLK UCA0BR0 = 0x09; // 1MHz 115200 UCA0BR1 = 0x00; // 1MHz 115200 UCA0MCTL = 0x02; // Modulation UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine** IE2 |= UCA0RXIE; // Enable USCI_A0 RX interrupt _BIS_SR(LPM0_bits + GIE); // Enter LPM0, interrupts enabled } // Echo back RXed character, confirm TX buffer is ready first #pragma vector=USCIAB0RX_VECTOR __interrupt void USCIA0RX_ISR (void) { while(!(IFG2&UCA0TXIFG)); UCA0TXBUF = UCA0RXBUF; // TX -> RXed character }